Status Job Pipeline Stage Commit Msg Timing Output
           
Samples
  • ia32 aaa
  • ia32 adc al,0x12
  • ia32 adc ax,0x1234
  • ia32 adc byte [ax],0x12
  • ia32 adc word [ax],0x1234
  • ia32 add ax,bx
  • risc-v auipc a0,0x18000
  • risc-v addi a0,a0,0x0
  • risc-v lui a2,0x40003
  • risc-v c.andi a3,a3,2
  • risc-v c.beqz a3,18
  • risc-v jal ra,0x6
00000000
00000010
00000020
00000030
33 10 01 00 33 10 01 00 33 10 01 00 33 10 01 00
33 10 01 00 33 10 01 00 33 10 01 00 33 10 01 00
33 10 01 00 33 10 01 00 33 10 01 00 33 10 01 00
33 10 01 00 33 10 01 00 33 10 01 00 33 10 01 00

		
RISC-V   IA32   Show error only
Reverse the bytes to input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
funct7
rs2
rs1
funct3
rd
opcode
I
imm
rs1
funct3
rd
opcode
S
imm[11:5]
rs2
rs1
funct3
imm[4:0]
opcode
B
imm[12|10:5]
rs2
rs1
funct3
imm[4:1|11]
opcode
U
imm[31:12]
rd
opcode
J
imm[20|10:1|11|19:12]
rd
opcode
 
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CR
funct4
rd/rs1
rs2
op
CI
funct3
imm
rd/rs1
imm
op
CSS
funct3
imm
rs2
op
CIW
funct3
imm
rd
op
CL
funct3
imm
rs1
imm
rd
op
CS
funct3
imm
rs1
imm
rs2
op
CB
funct3
offset
rs1
offset
op
CJ
funct3
jump target
op
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